Modules
	BSP Audio Out Option
	BSP Audio Sample Rate
Defines
#define	AUDIO_SAIx SAI1_Block_A
#define	AUDIO_SAIx_CLK_ENABLE() __HAL_RCC_SAI1_CLK_ENABLE()
#define	AUDIO_SAIx_CLK_DISABLE() __HAL_RCC_SAI1_CLK_DISABLE()
#define	AUDIO_SAIx_MCK_SCK_SD_FS_AF GPIO_AF13_SAI1
#define	AUDIO_SAIx_MCK_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define	AUDIO_SAIx_MCK_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
#define	AUDIO_SAIx_MCK_PIN GPIO_PIN_8
#define	AUDIO_SAIx_MCK_GPIO_PORT GPIOB
#define	AUDIO_SAIx_FS_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define	AUDIO_SAIx_FS_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
#define	AUDIO_SAIx_FS_PIN GPIO_PIN_9
#define	AUDIO_SAIx_FS_GPIO_PORT GPIOB
#define	AUDIO_SAIx_SCK_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define	AUDIO_SAIx_SCK_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
#define	AUDIO_SAIx_SCK_PIN GPIO_PIN_8
#define	AUDIO_SAIx_SCK_GPIO_PORT GPIOA
#define	AUDIO_SAIx_SD_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define	AUDIO_SAIx_SD_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
#define	AUDIO_SAIx_SD_PIN GPIO_PIN_1
#define	AUDIO_SAIx_SD_GPIO_PORT GPIOC
#define	AUDIO_SAIx_DMAx_CLK_ENABLE() __HAL_RCC_DMA2_CLK_ENABLE()
#define	AUDIO_SAIx_DMAx_CLK_DISABLE() __HAL_RCC_DMA2_CLK_DISABLE()
#define	AUDIO_SAIx_DMAx_REQUEST DMA_REQUEST_SAI1_A
#define	AUDIO_SAIx_DMAx_CHANNEL DMA2_Channel2
#define	AUDIO_SAIx_DMAx_IRQ DMA2_Channel2_IRQn
#define	AUDIO_SAIx_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD
#define	AUDIO_SAIx_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD
#define	DMA_MAX_SZE (uint32_t)0xFFFF
#define	AUDIO_SAIx_DMAx_IRQHandler DMA2_Channel2_IRQHandler
#define	AUDIO_OUT_IRQ_PREPRIO 5 /* Select the preemption priority level(0 is the highest) */
#define	AUDIO_SAIx_PLL_DISABLE() HAL_RCCEx_DisablePLLSAI1()
#define	AUDIO_DFSDMx_LEFT_CHANNEL DFSDM1_Channel4
#define	AUDIO_DFSDMx_RIGHT_CHANNEL DFSDM1_Channel3
#define	AUDIO_DFSDMx_LEFT_FILTER DFSDM1_Filter0
#define	AUDIO_DFSDMx_RIGHT_FILTER DFSDM1_Filter1
#define	AUDIO_DFSDMx_CLK_ENABLE() __HAL_RCC_DFSDM1_CLK_ENABLE()
#define	AUDIO_DFSDMx_CLK_DISABLE() __HAL_RCC_DFSDM1_CLK_DISABLE()
#define	AUDIO_DFSDMx_CKOUT_DATIN_AF GPIO_AF6_DFSDM1
#define	AUDIO_DFSDMx_CKOUT_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
#define	AUDIO_DFSDMx_CKOUT_CLK_DISABLE() __HAL_RCC_GPIOF_CLK_DISABLE()
#define	AUDIO_DFSDMx_CKOUT_PIN GPIO_PIN_10
#define	AUDIO_DFSDMx_CKOUT_GPIO_PORT GPIOF
#define	AUDIO_DFSDMx_DATIN_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define	AUDIO_DFSDMx_DATIN_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
#define	AUDIO_DFSDMx_DATIN_PIN GPIO_PIN_0
#define	AUDIO_DFSDMx_DATIN_GPIO_PORT GPIOC
#define	AUDIO_DFSDMx_DMAx_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE()
#define	AUDIO_DFSDMx_DMAx_CLK_DISABLE() __HAL_RCC_DMA1_CLK_DISABLE()
#define	AUDIO_DFSDMx_DMAx_LEFT_CHANNEL DMA1_Channel4
#define	AUDIO_DFSDMx_DMAx_RIGHT_CHANNEL DMA1_Channel5
#define	AUDIO_DFSDMx_DMAx_LEFT_IRQ DMA1_Channel4_IRQn
#define	AUDIO_DFSDMx_DMAx_RIGHT_IRQ DMA1_Channel5_IRQn
#define	AUDIO_DFSDMx_DMAx_LEFT_REQUEST DMA_REQUEST_DFSDM1_FLT0
#define	AUDIO_DFSDMx_DMAx_RIGHT_REQUEST DMA_REQUEST_DFSDM1_FLT1
#define	AUDIO_DFSDMx_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_WORD
#define	AUDIO_DFSDMx_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_WORD
#define	AUDIO_DFSDM_DMAx_LEFT_IRQHandler DMA1_Channel4_IRQHandler
#define	AUDIO_DFSDM_DMAx_RIGHT_IRQHandler DMA1_Channel5_IRQHandler
#define	AUDIO_IN_IRQ_PREPRIO 6 /* Select the preemption priority level(0 is the highest) */
#define	AUDIODATA_SIZE 2 /* 16-bits audio data size */
#define	AUDIO_OK 0
#define	AUDIO_ERROR 1
#define	AUDIO_TIMEOUT 2
#define	DEFAULT_AUDIO_IN_FREQ BSP_AUDIO_FREQUENCY_16K
#define	DEFAULT_AUDIO_IN_BIT_RESOLUTION 16
#define	DEFAULT_AUDIO_IN_CHANNEL_NBR 2 /* Mono = 1, Stereo = 2 */
#define	DEFAULT_AUDIO_IN_VOLUME 64
#define	INTERNAL_BUFF_SIZE 256
#define	CODEC_RESET_DELAY 5